Update from 25.08.2010: New facts on Bulldozer and Bobcat
New films from AMD confirms more details on Bulldozer and Bobcat. Besides the size of the L1 caches (64 per module KiByte for instructions per core 16 KiByte for data) is now officially announced that the L2 cache of a dual module will take two MiByte. The Data Translation Lookaside Buffer vollassoziativ works.
In addition to the SSE instruction set extensions 4.1 and 4.2 also AVX including AES (Advanced Encryption Standard) support. AES accelerates the encryption and decryption and is already supported by Intel and several Gulftown Arrandale and Clarkdale CPUs.
By sharing some components of a dual-module course is a little power is lost. AMD talks of achieving an average of about 80 percent of the power to two separate cores – in a cost-and energy-efficient design. Depending on the power to Bulldozer cores are also dynamically overclocked using the standard clock out “” – with a higher flexibility than they were in Thuban CPUs.
Bobcat SSE1 the instruction set extensions, SSE2, SSE3, SSSE3 SSE4a and will support and over 32 KiByte L1 data cache (8-way associative) and have 512 KiByte L2 cache (16-way associative) per core.
To save energy, the L2 cache that about 40 percent of the area occupied a Bobcat core, referred to only at half the clock frequency. In a failed branch prediction to 13 clock cycles pass, loading from the L1 or L2 cache and 17 require three clock cycles. From low-power support and C6-Core power gating AMD is hoping for a low power consumption.
Original article from 24/08/2010: Official information about AMD’s CPU architecture for 2011
As part of the 22 to 24 August held Hot Chips conference at Stanford University, AMD Official presented to the CPU architectures Bulldozer and Bobcat – including little new, but still much that is familiar or renewed Confirmed, suggesting that in view of the market currently only fine Tuning is present.
Bulldozer
Zambezi – the name of the desktop offshoot of four to eight cores is coming – for Socket AM3 + (not AM3), supports DDR3 RAM and is fabricated in 32-nanometer process.
AMD Bulldozer attesting to the current server-CPU-series Magny Cours due to an increase in nuclear number by a third round 50-percent power increase.
Whether the additional power besides nuclear proliferation rather different clock rates or architectural optimizations can be counted, is not yet known.
One of the main changes concerns the basic structure of the processor, which will be composed of modules, each with two cores. Eight-core versions of Zambezi thus consist of four dual core modules, which will access a shared L3 cache and memory.
Within the modules share the two cores, the control logic, probably 1-2 MiByte large L2 cache, which consisted of two 128-bit floating point unit FMAC units. It can be fully taken as needed from a core benefit.
Bobcat
Another goal pursued as a bulldozer with AMD Bobcat. This architecture is aimed at mobile devices and energy-efficient compact computer.
This is to use one – that is successful the official AMD presentation does not disclose – to 40 nanometers reduced feature size and an efficient construction: AMD talks vaguely of it, 90 percent of the power reaching the current middle-class CPUs with less than half the chip area to be able to.
Bobcat is only one part of the APU (Accelerated Processing Unit), code-named Ontario. The term APU points out that sitting in accordance with the merger concept, in which the CPU and a Direct-X-11-capable GPU that will run faster especially floating point calculations.
Bobcat has Intel’s low-power Atom chip well ahead, including the ability to send commands out-of-order execution, not necessarily in order of receipt of the work off. A higher per-MHz processing power is therefore likely. Especially economical versions of the Bobcat core will require less than one watt.
Source:http://www.pcgameshardware.de/aid,769009/Bulldozer-und-Bobcat-Offizielle-Infos-zu-AMDs-CPU-Architekturen-fuer-2011-Neue-Fakten/CPU/News/
